Title: Enabling the Design of Energy-Efficient and Reliable Processor Chips
Time：2018.10.22 Monday 2:30-3:30 pm
place：Room 502, Software building
Abstract:Power has been a primary challenge in the design of current and future processor chips. Reducing supply voltage VDD is a popular way to meet power budgets, which can be achieved by either decreasing nominal supply voltage VDD aggressively with technology scaling, or by applying runtime power saving techniques such as dynamic voltage scaling (DVS). In this talk, I will present two related topics: 1) energy-efficient processor chip design using DVS technique enabled by integrated voltage regulators and 2) reliable chip power supply with the aid of emergency detection system. In particular, I will present a few examples to show how machine learning techniques can be used to build such an emergency detection system.
Bio:Pingqiang Zhou received the M.E. degree from Tsinghua University, Beijing, China and a Ph.D. degree from the University of Minnesota. He has been an assistant professor with the School of Information Science and Technology at ShanghaiTech University, Shanghai, China. He was with the University of California, Berkeley as a visiting scholar in 2015.
Dr Zhou’s research interests include computer architecture, VLSI design automation, intelligent chip design and hardware security. He is serving on the technical program committee/as session chairs of top conferences such as DAC, ICCAD and ASP-DAC, and is also the invited reviewer for many top journals and conferences in the areas of VLSI design automation, computer architecture and VLSI design.